1. Field of the Invention
The present invention relates to a semiconductor memory device and more particularly to an electrically erasable and programmable non-volatile memory device, namely, an electrically erasable and programmable read only memory, called an EEPROM hereinafter.
2. Description of the Related Art
Generally speaking, an EEPROM receives a chip enable signal CE, an output enable signal OE or a write enable signal WE as a control signal, and determines various modes for waiting, erasing, writing or reading based on the logical state of those signals. However, these control signals CE, OE and WE are apt to be affected by variations in power source voltage or noise, and their logical states are thus confused by the variations in power source voltage or noise. As a result, sometimes a writing mode is accidentally set and error data is written, thereby resulting in an erroneous writing operation. Such erroneous writing can be avoided by providing a so-called software data protection circuit within the memory device.
Conventionally, an EEPROM equipped with a software data protection circuit, as shown in FIG. 1, is utilized.
In FIG. 1, the EEPROM comprises a row-decoder 1, a cell matrix 2, a read column decoder 3, a read column gate 4, a sense amplifier 5, an I/O buffer 6, an E/W (erase/write) column decoder 7, an E/W column gate 8 and a page register 9. It further comprises a control signal logic circuit 10, an E/W timing signal generating circuit 11, an increased voltage generating circuit 12, and a software data protection circuit 13.
In such an EEPROM, the chip enable signal CE, the output enable signal OE and the write enable signal WE are put in the state shown in the following table 1, thereby enabling the EEPROM to be set in the write mode.
TABLE 1 ______________________________________ ##STR1## ##STR2## ##STR3## ______________________________________ L H ##STR4## ______________________________________
In this write mode, as shown in FIG. 2, the write address is obtained at the fall of the write enable signal WE and the write data is obtained at the rise of the write enable signal WE. However, a combination of the logical values of control signals CE, OE and WE for setting the write mode is sometimes wrongly set by the variation in power source voltage and noise, as described above. The software data protection circuit 13 is for preventing an erroneous write operation as caused by that described above. Software data protection circuit 13 has an EEPROM cell 13A, which sets a software data protection circuit 13 to prevent the data from being written in respective memory cells in cell matrix 2 by setting storing and maintaining a discretional logic value in EEPROM cell 13A. An address signal of 16 bits comprising, for example, the row-address and column-address input to matrix 2 and the data output from I/O buffer 6, are input to the software data protection circuit 13. The software data protection is set by sequentially providing the address and the data to the software data protection circuit 13.
That is, in the software data protection circuit 13, a writing operation is performed for the EEPROM cell 13A when (1) address=5555, data AA, (2) address=2AAA, data=55, and (3) address=5555, data=A0 are sequentially input to the software data protection circuit 13. The address and data will be expressed by a hexadecimal notation herein. Then logic "0" (conduction state) is set in the EEPROM cell 13A, thereby setting, storing and maintaining a software data protection state. Thereafter, when this state is not released, providing the address and data for setting the software data protection is not input to that circuit 13, (i.e., providing write data is not input to the circuit 13 following the address and data for setting the software data protection is not input thereto) the increased voltage VPP necessary to write the data in respective EEPROM cells forming cell matrix 2 is prevented from being output from the increased voltage generating circuit 12, thereby preventing the data from being written into respective memory cells in cell matrix 2.
Therefore, when such a software data protection circuit 13 is provided, even if the logic state of the above control signals CE, OE and WE are incorrectly set by the variations in the power source voltage or noise and correspondingly logic circuit 10 for a control signal is set write mode incorrectly, the increase voltage Vpp is not applied to a control gate of respective EEPROM cell forming cell matrix 2. Thus, the data is prevented from writing into respective EEPROM cells of cell matrix 2.
When (1 ) address=5555, data=AA, (2) address=2AAA, data=55, (3) address=5555, data=10, (4) address=5555, data=AA, (5) address=2AAA, data=55, and (6) address=5555, data=20 are sequentially input to the software data protection circuit 13, a deletion operation is performed for EEPROM cell 13A. A logic "1" (non conductive state) is set in EEPROM cell 13A and thus the software data protection testing state is removed.
As described above, in a conventional EEPROM, when the software data protection state is set, data is not written in cell matrix 2 if an address and data for setting the software data protection is not input to EEPROM cell 13A. In other words, the software data protection state is set, the write operation is performed for EEPROM cell 13A whenever the data is written into cell matrix 2. When write mode is set, a write operation is not performed to all the EEPROM cells forming cell matrix 2. Namely, when the setting and releasing operations of software data protection are frequently performed, the writing operation for the EEPROM in the software data protection circuit 13 is performed more than that for the writing operation for the discretional EEPROM cell 13A.
In a write mode, a write operation is not carried out for all the EEPROM cells forming a cell matrix 2. Namely, the number of a write operations by which data is written in EEPROM 13A in the software data protection circuit 13 is sometimes larger than that of write operations by which data is written in other EEPROM cell forming cell matrix 2.
Therefore, in the conventional EEPROM, there is a problem that EEPROM cell 13A forming the software data protection circuit 13 deteriorates faster than the EEPROM cell forming the cell matrix 2 deteriorates.